The present invention relates to a semiconductor integrated circuit (i.e., a semiconductor device) testable by a test system even when the semiconductor integrated circuit operates faster than the test system.
A test technique, called dynamic burn-in testing, for accelerating the aging of semiconductor devices has been known in the art. The purpose of a dynamic burn-in test operation is to remove or screen out devices that are subject to time and stress-dependent failures. More specifically, such a screening-out operation is carried out by applying a supply voltage in excess of the rated voltage to a test-target device at constant temperature while applying to the device an input signal similar to one that is applied in the normal operation. A monitored burn-in system has, in addition to a dynamic burn-in function, a device output monitoring/observing function.
With the speed-up of the operation of semiconductor devices, their maximum operation frequency has increased. Japanese Unexamined Laid-Open Patent Application Publication No. 6-187797 discloses a technique. In accordance with the 6-187797 technique, in order to enable a slow test system to perform testing of a fast memory device, the frequency of an external clock signal is increased in the inside of the memory device for generating an address signal in synchronization with an internal clock signal having the increased frequency. However, the 6-187797 technique makes no disclosure of the monitoring of device output.
In accordance with the monitored burn-in system described above, the monitoring of the output of the device is repeatedly carried out at given time intervals. However, during the device output monitoring, there occurs a drop in voltage stress because the supply voltage of the device is lowered down to the rated voltage. Accordingly, there has been strong demand for reductions in the time required for each monitoring operation. To satisfy such demand, the devices are required to operate at a high speed as required in their normal operation if they are capable of high-speed operation, even during the device output monitoring under burn-in testing. However, because of the various limits of test systems, the devices, although they have the capability of operating at a high speed, are practically forced to operate at a lower speed during the device output monitoring under burn-in testing.
The operation of monitoring device outputs is indispensable also to functional testing of high-speed devices. However, such a device output monitoring operation has been beyond the capability of a low-speed test system.
Accordingly, an object of the present invention is to make it possible for a slow-speed test system to perform monitoring of the output of a high-speed device.
In order to achieve the object, in the present invention, the variation frequency that the output of a high-speed device varies is lowered in the inside of the device, whereby a signal, whose variation frequency is low, can be provided from the device.
In one aspect, it is a feature of the present invention to provide a first semiconductor device that employs a configuration comprising (a) a functional circuit for providing, in synchronization with a clock signal, data at a first frequency, (b) data holding means for performing a data take-in/hold operation so that in a first period of cycles having the first frequency within one period of cycles having a second frequency lower than the first frequency, first data is taken in from the functional circuit and held in the data holding means, (c) data taking-in means for taking in, from the functional circuit, second data in a second period of the cycles having the first frequency posterior to the first cycle within the period of cycles having the second frequency, and (d) data output converting means for generating, based on the first data held in the data holding means and the second data taken in by the data taking-in means, third data and for providing the third data at the second frequency. By virtue of the configuration described above, of the data outputs from the functional circuit at the first frequency, the first data in one period of the first frequency and the second data in another period of the first frequency are provided to the data output converting means. The data output converting means generates, based on both the first data and the second data, the third data and provides it at the second frequency lower than the first frequency. This accordingly enables even a slow test system to monitor the output of the device. In order for the test system to perform a device output monitoring operation with efficiency, the data output converting means performs a data conversion operation so that the number of states assumable by the third data falls below the number of all possible combinations of states assumable by the first data and states assumable by the second data.
In another aspect, it is a feature of the present invention to provide a semiconductor integrated circuit having a normal operation mode and a test mode. This semiconductor integrated circuit employs a configuration comprising (a) a functional circuit for providing a two-valued logic signal which varies at a predetermined variation frequency, (b) a converting circuit for converting the two-valued logic signal supplied from the functional circuit into a multiple-valued logic signal which varies at a less variation frequency than that of the two-valued logic signal, and (c) an output selecting circuit for selecting between the two-valued logic signal and the multiple-valued logic signal, wherein when the semiconductor integrated circuit is in the normal operation mode, the output selecting circuit selects the two-valued logic signal as a signal to be provided from the semiconductor integrated circuit and wherein when the semiconductor integrated circuit is in the test mode, the output selecting circuit selects the multiple-valued signal as a signal to be provided from the semiconductor integrated circuit. The foregoing multiple-valued logic signal is a three-valued logic signal having, in addition to a high voltage level state representative of a logical value of 1 and a low voltage level state representative of a logical value of 0, a high impedance state representative of a third logical value. The configuration described above makes it possible for even a slow test system to monitor the output of the device. In addition, the amount of information transferable by multiple-valued logic signals per unit time in the test mode (a first information rate) can be increased to such an extent that the first information rate equals a second information rate (the amount of information transferable by two-valued logic signals per unit time in the normal operation mode). It is however possible to select how many logic value levels a multiple-valued logic signal should assume and how frequently it should vary so that the second information rate falls below the first information rate.